1. Field
The embodiments discussed herein are directed to semiconductor devices and manufacturing methods of semiconductor devices, which may have trench capacitors, in which the semiconductor devices include CMOS logic circuits and one transistor-one capacitor type memory cells formed on the same substrate, and the memory cells utilize side walls of shallow trench isolation (STI) for memory capacitors and a manufacturing method of the semiconductor device.
2. Description of the Related Art
For semiconductor memories that include memory cells to store data in capacitors, trench capacitor type semiconductor memories are proposed for reducing the cell area and increasing integration of the semiconductor devices, in which shallow trench isolation (STI) is used for capacitors formed by using side walls of the trenches, and insulating films on the bottom of the STI trenches isolate adjacent memory cells (see Patent Reference 1).
A conventional trench capacitor includes a cell plate provided on a dielectric film formed on a side wall of a trench and a semiconductor substrate, in which an impurity diffusion layer is provided on a surface side of a silicon substrate located between a transfer transistor and the cell plate electrode. The capacitor connected to the source-drain diffusion region of the transfer transistor is formed by applying a bias voltage to the cell plate electrode to invert a channel of the substrate surface.
For further increase in integration of semiconductor memory devices, the width of device isolation (STI: shallow trench isolation) is predicted to be narrowed in the future. A size reduced device structure may be provided with trenches that are fully filled with cell plate electrodes.
FIG. 1 shows a trench capacitor type memory cell with size reduction. For this memory cell, an inversion layer 105 is formed by applying a bias to a cell plate (CP) electrode 106 from the surface of a silicon substrate 101 toward a side wall of the trench 102. A buried insulating film 103 located on the bottom of the trench 102 isolates a memory cell from an adjacent memory cell. The inversion layer 105 is connected to one end of LDD (lightly doped drain or extension) impurity diffusion region 108 extended toward one end of a word line (WL) 107, and forms a storage node of a capacitor. A source-drain impurity diffusion region 109 is connected to an upper bit line through a bit line contact (not shown).
In general, when an impurity concentration of the cell plate electrode 106 is low, a depletion layer expands from the interface between the dielectric film 103 and the cell plate electrode 106 to an inner part of the cell plate electrode 106 when a bias is applied, and this prevents forming an inversion layer and decreases the effective capacitance of the capacitor. The impurity concentration of the cell plate electrode 106 is preferred to be designed high enough to prevent forming the depletion layer when being biased.
However, for a configuration where the cell plate electrode 106 fills the trench 102 (STI), the impurity concentration at a deep region of the STI trench 102 becomes lower when ion implantation energy for introducing impurities into the cell plate electrode 106 is not high enough. This results in forming a depletion region A at an inner part of the cell plate electrode 106, so that a channel region is not easily inverted and the effective capacitance of the capacitor is reduced. As a result, it becomes a problem that a predetermined capacitance characteristic (data storage characteristics) is not obtained.
For this problem, there are possible solutions as follow:    (A) Thinning the cell plate electrode    (B) Increasing the energy of impurity implantation    (C) Introducing impurities during the cell plate electrode formationHowever, each solution above causes an increase in manufacturing steps, degradation of periphery transistor characteristics, and increase in leakage currents.
FIG. 2A shows a drawback related to thinning the cell plate electrode 106 (A). When the cell plate electrode 106 is thinned, the gate electrodes (word line: WL) of the periphery transistors become thinner. This is because, in general, the cell plate electrodes and the gate electrodes (or word line) of periphery transistors are formed in the same process step. When the gate electrode is formed thin, the ion implantation of a source-drain (SD) diffusion layer using the gate electrode needs to be shallow. This may cause degradation of periphery transistors. When a resistor is formed with the same layer as the gate electrode layer of the periphery transistors, the resistance of the resistor becomes high (not shown).
To avoid this drawback, the cell plate electrode (CP) may be formed separately from the gate electrodes (WL) of the periphery transistors. However, the number of the fabrication steps increases, which increases process difficulty of the fabrication.
FIG. 2B shows a problem related to method (B) of increasing ion implantation energy. When the implantation energy is increased, impurity penetration (arrow (a)) may occur underneath the gate electrodes (WL) of the periphery transistors. This may cause an increase in a junction leakage current and an increase in field leakage currents between adjacent capacitors.
When the ion implantation is performed for a trench capacitor part and a transistor gate part by using different resist patterns, the number of fabrication steps is increased. Further, margins need to be provided for the alignment of the resist patterning. This may induce impurity penetration. As a result, an unnecessary diffusion layer 120 is formed around side walls of the trench, which causes an increase in the leakage currents (arrow (b)) between the adjacent cells and degrades the field leakage characteristics.
FIG. 3 shows a matter of concern for the impurity doping during the cell plate electrode formation. A method (C) of doping impurities during film formation is known (e.g. Patent References 2, 3, and 4). However, the cell plate electrodes and the periphery transistors are formed in the same process. That does not allow providing different gates for the periphery transistors, and this limits the performance of the periphery transistors. For providing different gates for periphery transistors as shown in FIG. 3, for example, the forming steps of cell plate electrodes and gates of periphery transistors may be separated, however, difficulties arise.
First, the manufacturing cost would increase because the fabrication steps are complicated. As shown in FIG. 3(a), a gate oxide film 130 is formed on a silicon substrate 101, on which an n+-doped silicon film 131 is formed. In FIG. 3(b), a gate electrode 132 of an NMOS (n-type metal oxide semiconductor) transistor is formed by an etching process, and an n−-LDD 138 (n-type lightly doped drain) is formed only on the NMOS region by ion implantation. In this step, a gate oxide film 130 of a PMOS (p-type metal oxide semiconductor) transistor is exposed during the etching process, which may reduce reliability of PMOS transistors to damage due to over-etching of the etching process. In the next step, a p+-doped silicon film 133 is formed as shown in FIG. 3(c), and the impurities in LDD 138 of the NMOS region diffuse during the formation of p+-doped silicon film 133, which makes it difficult to maintain shallow junctions of the LDD 138 and may cause degradation of devices.
Further, as shown in FIG. 3(d), a PMOS gate electrode 134 is formed by the etching process, and impurities of a p−-LDD 139 are implanted onto only the PMOS transistor regions. In this step, part of the p+-doped silicon film 135 is left on the side walls of the gate electrode 132. As a result, the actual size of the NMOS gate electrode becomes longer, which makes the transistor area and the layout area larger. On the other hand, n+ source-drain diffusion region (SD) 140 is formed by using the p+-doped poly silicon film 135 as a mask. The distance between LDD 138 and SD 140 is limited by the thickness of the p+-doped poly silicon film 135. This distance increases the resistance, which becomes a disadvantage for high performance of the device. However, when the p+-doped poly silicon film 135 is formed to be thinner, the impurity implantation of SD 140 at the NMOS region cannot be formed deeply, which degrades the device performance.
As a final step, side walls 136 are formed, and followed by p+ source-drain regions (SD) 141 formation in PMOS regions.
As discussed above, the conventional process of introducing impurities during cell plate electrode film formation includes the complexity of the fabrication process and difficulty in applying the process to dual gate devices.
Without the electrode formation discussed above, there is another issue that requires reducing layout areas of resistors with size reduction of devices. Most peripheral circuits of memory cell drivers, logic circuits, and analog circuits include resistors, and individual circuits require different resistances of their resistors. For example, small current circuits require high-resistance resistors and fast operation circuits require low-resistance resistors.
In general, resistor elements are formed by implanting impurities into a poly silicon film or a silicon substrate. When the number of types of resistor elements (resistivity per unit area) is limited, a high resistance resistor may be formed with low resistivity resistor elements, and a low resistance resistor may be designed by using high-resistivity resistor elements. Thereby, the layout area is increased, as shown in FIG. 4.
As indicated in FIG. 4(a), when a high resistance resistor element is designed by using low-resistivity resistor elements, the layout area is increased as plural low-resistivity elements need to be connected in series. Likewise, when a low resistance element is designed by using plural resistance elements with high resistivity, the units need to be connected in parallel, so that the layout area is increased as shown in FIG. 4(b). Although it is preferred that plural types of resistor elements be built on a single substrate, additional fabrication processes are necessary for fabricating such resistor elements.    Patent Reference 1: Japanese Patent Application Publication No. 2003-92364    Patent Reference 2: Japanese Patent Application Publication No. 11-307737    Patent Reference 3: Japanese Patent Application Publication No. 2000-114458    Patent Reference 4: Japanese Patent Application Publication No. 2005-51045